Recently, as semiconductor devices are more highly integrated, a three dimensional package technology has been studied. Particularly, a through silicon via (TSV) technology have been widely studied. In the TSV technology, a via hole is formed through a silicon substrate, and a through via is formed to fill the via hole. Further, a seed pattern may be formed on an inner wall of the via hole.
However, as an aspect ratio of the via hole increases, it is hard to form the seed pattern that includes good step coverage.